Documente Tehnice (Imaginile sunt cu titlu informativ. Va rugam sa consultati specificatiile tehnice.)
Specificatii
Marca
STMicroelectronicsProduct Type
Microprocessor
Series
STM32MP23xA/D
Device Core
ARM Cortex A35, ARM Cortex M33
Data Bus Width
16bit
Instruction Set Architecture
64 Bit, ARM V8-M, Arm Cortex
Maximum Clock Frequency
1.5GHz
Interfata
SPI, USART, UART, SAI, SPDIF, USB, SDM, I2C, FMC, MIPI-DSI, LVDS, CAN, DDR4, LPDDR4, DDR3L, Ethernet
Tip pachet
TFBGA361
Tensiune de alimentare minima
1.71V
Numar pini
361
Tensiune de alimentare maxima
3.6V
Standards/Approvals
JEDEC
Number of Cores
2
Automotive Standard
No
Tara de origine
Taiwan, Province Of China
Detalii Produs
The STMicroelectronics MPU with Arm Cortex-A35 devices are based on the high-performance single or dual-core Arm Cortex-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex‑A35 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU, and a 512-Kbyte L2 cache. The Cortex‑A35 processor uses a highly efficient 8 stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency.
Informatii despre stoc temporar indisponibile
P.O.A.
1
P.O.A.
Informatii despre stoc temporar indisponibile
1
Documente Tehnice (Imaginile sunt cu titlu informativ. Va rugam sa consultati specificatiile tehnice.)
Specificatii
Marca
STMicroelectronicsProduct Type
Microprocessor
Series
STM32MP23xA/D
Device Core
ARM Cortex A35, ARM Cortex M33
Data Bus Width
16bit
Instruction Set Architecture
64 Bit, ARM V8-M, Arm Cortex
Maximum Clock Frequency
1.5GHz
Interfata
SPI, USART, UART, SAI, SPDIF, USB, SDM, I2C, FMC, MIPI-DSI, LVDS, CAN, DDR4, LPDDR4, DDR3L, Ethernet
Tip pachet
TFBGA361
Tensiune de alimentare minima
1.71V
Numar pini
361
Tensiune de alimentare maxima
3.6V
Standards/Approvals
JEDEC
Number of Cores
2
Automotive Standard
No
Tara de origine
Taiwan, Province Of China
Detalii Produs
The STMicroelectronics MPU with Arm Cortex-A35 devices are based on the high-performance single or dual-core Arm Cortex-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex‑A35 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU, and a 512-Kbyte L2 cache. The Cortex‑A35 processor uses a highly efficient 8 stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency.